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Products Main

PCI-Xactor Test Environment

Complete solution to verify PCI Express 1.0a/1.1/2.0,3.0 (Gen3), SR-IOV, PIPE 2.0,3.0 components and peripherals.

  • Supports all protocols 1.1,2.0,3.0(Gen3) , SR-IOV, PIPE 2.0,3.0
  • Supports any PCI topology
  • Comprehensive BFM support including Root Complex, Endpoint, Switch
  • Endpoint, Switch, Bridge testbench frameworks ease integration of DUV and running compliance testsuites
  • Supports active test generation and passive SuperMonitor link monitoring
  • Comes with compliance test suites based on PCISIG checklists and test specifications
  • High-level PCI transaction API supports Verilog, SystemVerilog, Specman, Vera, SystemC, C/C++, and
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  • Protocol verifiers check and reports all PCI Express/PCI-X/PCI compliance violations
  • Functional coverage monitor reports device and command utilization

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USB-Xactor Test Environment

Your Solution to Sperrspeed USB 3.0 Compliance Validation

  • Complete solution for core through chip-level verification
  • Superspeed USB3.0 and 2.0 OTG
  • UTMI, PIPE
  • xHCI
  • Comprehensive model support – Host, Device, Hub, PHY
  • Comprehensive compliance testsuite for Protocol, Link, and Physical layer verification
  • Supports Verilog and SystemVerilog OVM/VMM environments
  • Delivered in SystemVerilog source code

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SATA-Xactor Test Environment

Complete solution to verify SATA/PATA/AHCI components and peripherals.

  • Verify SATA 1/2/3, ATA/ATAPI-7/8, components
  • AHCI 1.2 PCIe and AHB/AXI drivers
  • Complete BFM support - Host and Device models
  • Supports active test generation and passive link monitoring
  • Supports many environments - Verilog, SystemVerilog, Specman, Vera, SystemC, C/C++, and VHDL
  • Over 500 protocol checkers verify compliance and reports violation.
  • DMA setup supports memory buffer/descriptor allocation, initialization, and read-verify operations
  • Disk store back-end model using sparse sector-based implementation
  • Back-door read/write to host memory and disk sectors
  • Control device response behaviors including request completion times
  • Inject errors and noise at various layers
  • Supports power management including hot-plug
  • Serial and SAPIS interface supported

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Insight :Simulation-Centric Formal Analysis


First behavioral-level formal analysis tool for verilog and SystemVerilog
Describe interface protocols and design properties using behavioral-level testbench with minimal random constraints,reference models, and properties vs complex RT - level methods.
Eliminate major development effort to write constraints guiding coverage test generation for corner cases.
Support reference model based methodologies which greately improve scalability of formal analysis.
Tightly integrated simulation and formal engines provide simulation-centric feel and better control over case analysis and refinement.
More efficient for both designers and verification engineers

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SimCluster - Parallel Simulation

Distributed parallel simulation speeds up system-level simulation by 500% - 1,500%.

  • Increase RTL and gate-level simulation performance and capacity by 5-15 X
  • Supports gate-level simulation with full SDF back-annotation
  • Integrated flow with popular ATPG tools for rapid validation of scan and BIST vectors
  • Supports popular computing solutions of 2 to 10s of computers
  • Alternative to hardware acceleration solutions
  • Advanced behavioral and gate-level auto-partitioning
  • Trade-off signal-level versus transaction-level accuracy for improved performance
  • Works with most Verilog and VHDL simulators


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AMBA - AXI/AHB

The AMBA-Xactor supports verification of AMBA-based designs using the AXI 3.0 and AHB 2.0 standards.
AMBA-Xactor allows users to verify their designs by developing directed and constrained random custom tests.


• Master, Slave, and Interconnect models
• Slave supports simple memory and FIFO models
• Supports random wait states on address, data, and response channels including programmable
response behavior using request matching
• Supports data interleaving and multiple outstanding requests
• Supports out of order response
• Supports exclusive access and locked transactions
• Master supports read-verify operation

 

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